Counter with non-uniform digit base

ABSTRACT

A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.

FIELD OF THE INVENTION

[0001] The present invention relates generally to electronic counters,and more specifically to a non-volatile counter with a non-uniform digitbase.

BACKGROUND OF THE INVENTION

[0002] Non-volatile counters are used in various electronicapplications. One important application for non-volatile counters is inthe field of electronic commerce where it is important to orderfinancial transactions in a definite sequence. In such applications itis important that the counting function be robust enough to withstandhardware and/or software failures, including unexpected power loss. Itis also important for the counting function to be secure againstunauthorized access and tampering.

[0003] One technique for providing a counting function that canwithstand power loss is to use a battery or similar power supply inconjunction with a binary counter circuit. Unfortunately, battery-backedcounters tend to occupy a relatively large amount of circuit or devicespace and impose high battery costs. Also, batteries are prone tofailure and discharge and so must be monitored and periodically replacedto prevent loss of the count data. Further, many binary counters do notallow for easy recovery of count data in the event of count interruptiondue to power loss.

SUMMARY OF THE INVENTION

[0004] A counter is disclosed. The counter includes a nonvolatilestorage organized in digits having non-uniform bases and circuitry toincrement a count value represented by the digits in response to anincrement command.

[0005] Other features and advantages of the present invention will beapparent from the accompanying drawings and from the detaileddescription that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements, and in which:

[0007]FIG. 1 is a block diagram of a computer system in which a counteraccording to embodiments of the present invention may be used;

[0008]FIG. 2 illustrates an exemplary digit counter that includes Nbase₁₀ digits;

[0009]FIG. 3 illustrates a nonvolatile memory device in which a digitcounter having nor-uniform digit bases has been implemented according toone embodiment;

[0010]FIG. 4 illustrates further details of the nonvolatile memorydevice of FIG. 3 according to one embodiment;

[0011]FIG. 5 depicts an exemplary list of commands supported by thecommand nonvolatile memory device of FIG. 4; and

[0012]FIG. 6 is a flow diagram of an increment operation performed by acommand state machine in a nonvolatile memory device according to oneembodiment.

DETAILED DESCRIPTION

[0013] A counter with a non-uniform digit base is described in variousembodiments. In one embodiment, the counter is implemented in anonvolatile memory device so that the count value is maintained duringpower loss. The base of each digit in the counter is selected inaccording to application requirements and characteristics of thenonvolatile memory device.

[0014]FIG. 1 is a block diagram of a computer system 100 in which acounter according to embodiments described herein may be used. Thecomputer system 100 includes a processor 102 coupled through a bus 101to a memory 104 and a mass storage device 106. Memory 104 may be randomaccess memory (“RAM”), read-only memory (“ROM”), or other non-volatilememory, such as flash memory. Mass storage device 106 may be a largecapacity persistent storage device, such as a hard disk drive, tapedrive, or CD-ROM drive. An input/output controller 108 is coupled to bus101 for receiving commands or data entered through a keyboard, mouse, orsimilar input device. A display device controller 112 is also coupled tobus 101 for providing output through an appropriately coupled displaydevice 114.

[0015] Computer system 100 also includes a security co-processor 110.Security co-processor 110 is an embedded controller that includesdigital circuits to execute security programs and perform mathematicaltransforms for security. Security co-processor 110 includes severalcircuits that perform security functions, such as authenticationcircuits and random number generators. Security co-processor 110 alsoincludes counter 116, implemented according to embodiments describedherein, to enable authentication and unique identification of thetransactions that occur within the system. The ability to authenticateand uniquely identify transactions provides a level of security inprotecting the transactions from tampering by unauthorized parties. Themonotonic counter 116 may be used in other computer architectures anddevices without departing from the spirit and scope of the presentinvention.

[0016] In one embodiment, the counter 116 is a monotonic counterimplemented in a flash EPROM (erasable programmable read-only memory). Amonotonic counter is a counter that counts in one direction only, up ordown. The flash EPROM used to implement the monotonic counter may beintegrated with the circuitry for the security co-processor 110 (i.e.,on the same chip), or implemented in a separate device. Flash EPROMdevices typically use a single-transistor memory cells to store data.The state of a given cell is changed by program (1→0) and erase (0→1)operations which may be initiated by processor 102 or by securityco-processor 110.

[0017] Counters in electronic circuits typically count in binary, witheach bit representing a base two digit in the count value. Onecharacteristic of such binary counters is that each bit in the countchanges state twice as frequently as the next more significant bit, withthe least significant bit in the count changing state with each countincrement. In the context of a non-volatile memory, this toggling of theleast significant bit significantly limits the count rate that can beachieved because a relatively slow erase cycle is required every othercount. For example, for a typical flash memory cell, the program cycletime may be on the order of 10 microseconds, whereas the erase cycletime may be on the order of one second. In this case, the average countrate for the binary counter is limited to approximately one half secondper count increment (i.e., (1E−5 sec+1 sec)/2). Such a slow averagecount rate is inadequate for many types of counting applications.

[0018] Another problem that results when a binary counter is implementedin a non-volatile memory is that the frequent programming and erasing oflow-order bits may quickly exceed the maximum number of program/erasecycles that can be performed on the memory cell before the cell becomesunusable. For example, in a flash memory device, the continuousprogramming and erasure of the cells leads to stress and eventualbreakdown of the oxide layer in the memory cells. Advanced processingtechniques have produced flash EPROM devices that permit on the order of100,000 program/erase cycles before cells begin breaking down. Thus, themaximum number of program/erase cycles supported by a particular memorydevice may limit the maximum count of a binary counter implemented inthe device and therefore may render the binary counter unsuitable forcertain applications.

[0019] In one embodiment, the above described maximum count and countrate problems are addressed by a “digit counter” implemented in anon-volatile memory device. The count value of a digit counter isindicated by a plurality of digits, with each digit having a number ofbits equal to the base of the digit minus 1. For example, the tensymbols of a base₁₀ digit may be represented by nine bits as follows:Symbol Digit 0 111111111 1 111111110 2 111111100 3 111111000 4 1111100005 111100000 6 111000000 7 110000000 8 100000000 9 000000000

[0020] A significant benefit of this arrangement is that each of the Nsymbols of a base_(N) digit may be represented by incrementally changingonly one bit of the N−1 bits of the digit. In the context of anon-volatile memory device, this means that only one erase cycle need beperformed every N counts (i.e., to wrap around from all zeros to allones). This is in contrast to a typical binary counter in which an erasecycle must be performed every other cycle. Because there are fewer timeconsuming erase cycles, a higher average count rate and a higher countlimit can be achieved.

[0021]FIG. 2 illustrates an exemplary digit counter 22 that includes Nbase₁₀ digits. Because an erase cycle (i.e., restoring bits from 0 to 1)is required only every 10^(th) count, as opposed to every second countin a standard binary counter, the average count rate achievable in thedigit counter 22 is approximately five times that of a standard binarycounter. Similarly, because a program/erase cycle occurs only once every10^(th) count, as opposed to once every other count in a standard binarycounter, the maximum count limit of the digit counter 22 isapproximately five times that of a standard binary counter.

[0022] Generalizing from the digit counter 22 illustrated in FIG. 2, anerase cycle is required as frequently as the least significant digit ofthe count must be rolled over. Roll over of the least significant digit,on the other hand, is a function of the base of the digit. Combiningthese two concepts yields that the erase cycle frequency in a digitcounter is inversely related to the base of the least significantdigit—by increasing the base, M, of the least significant digit, theerase cycle frequency is reduced. This result is exploited to advantagein a preferred embodiment of a digit counter by having a leastsignificant digit with a relatively large base and higher order digitswith relatively small bases. The bases of the higher order digits do notinfluence the erase cycle frequency in the same way as the leastsignificant digit and thus can be made smaller to save storage (recallthat the number of bits required to represent the digit is determined bythe base of the digit). In an alternate embodiment, however, the basesof the higher order digits may also be made large.

[0023]FIG. 3 illustrates a nonvolatile memory device 25 in which a digitcounter 27 having non-uniform digit bases has been implemented accordingto one embodiment. The least significant digit, DIGIT1, has a relativelylarge base (base=65536), while the more significant digits, DIGIT2 andDIGIT3, have somewhat smaller bases (base=1024). Because of the largebase of the least significant digit, the maximum average count rate ofthe digit counter 27 is significantly faster than a binary counter thatrequires an erasure cycle every other count (i.e., approximately 65536/2times as fast) and the number of program/erase cycles required to reacha given count is similarly reduced. The maximum count value that-can bereached by the digit counter is the product of the bases of its threedigits (65536*1024*1024=6.87*10¹⁰), which is adequate for a broad rangeof counting applications. Of course, because of its larger base, DIGIT1consumes more memory (8 kilobytes) than DIGIT2 and DIGIT3 (128 byteseach), but such storage requirements can be accommodated by manycommercially available nonvolatile memory devices (e.g., flash EPROM andother forms of programmable non-volatile memory). Also, to ensuremonotonic operation of the digit counter, storage for the mostsignificant digit, DIGIT3, may be implemented in memory cells thatcannot be erased (e.g., one-time program (OTP) memory) to prevent thedigit counter from wrapping around. Additional circuitry may also beprovided to prevent wrap around of lower order digits after the maximumcount has been reached. Alternatively, wrap prevention of lower orderdigits after reaching the maximum count may be implemented in systemsoftware. For example, kernel level software may be executed to commandthe incrementing of the non-volatile digit counter so that, upondetecting that the maximum count has been reached, increment commandsare no longer issued. Note that there may be more or fewer digits in adigit counter according to an alternate embodiment. Also, the values ofthe digit bases shown in FIG. 3 are examples only. Digits having largeror smaller bases may be used in alternate embodiments.

[0024] In one embodiment, the base of the least significant digit isselected according to a maximum count and a minimum average count ratespecified for a given application. In essence, the base of the leastsignificant digit is made large enough to meet the minimum average countrate and also to ensure that the number of program/erase cycles requiredto reach the maximum count will not exceed the maximum number ofprogram/erase cycles specified for the non-volatile memory device inwhich the digit counter is to be implemented. More specifically, assumethat a given average count rate, R counts/sec, is required in a counterapplication. Then, the minimum digit base for achieving the averagecount rate may be determined by the following equation:

Min Digit1 Base=(Erase Time−Program Time)/((1/R−Program Time)

[0025] For example, assume that a minimum average count rate of 1000counts per second is required, that the erase time of the nonvolatilememory device is 1 second and that the program time is 10 microseconds.Then the minimum base of the least significant digit that could supportthe count rate is (1−1E−5)/(1E−3−1E−5)=1010.1, which rounds up to 1011.

[0026] The relation of the maximum count to the number of program/erasecycles of the implementing nonvolatile memory device may also dictatethe minimum base of the least significant digit. As discussed above, themaximum number of counts that be provided by a digit counter is equal tothe product of the bases of the counter's digits (or, more precisely,the product less 1). Because the least significant digit will be erasedonce for each increment (including rollover) of the next to leastsignificant digit, the number of erase cycles required to reach thecounter's maximum count is equal to the maximum count of the digitcounter divided by the base of the least significant digit (i.e.,product of bases of all digits except the least significant digit). Forexample, suppose that the 1000 count-per-second counter applicationrequires a maximum count of 20 billion (2E10), and that the nonvolatiledevice in which the counter is to be implemented permits a maximum of100,000 erase cycles. In this case, the next to least significant digitcan be incremented (including rollover) no more than 100,000 times inorder to reach the maximum count of 20 billion. Otherwise the maximumerase cycle specification of the nonvolatile memory device will beexceeded. Accordingly, the base of the counter must be at least 20billion/100,000=200,000, or approximately 25 kilobytes in size. Thus, inthis case, the maximum count required by the application and erase cyclelimitations in the implementing nonvolatile device determine the base ofthe least significant digit, not the count rate. To complete theexample, five base 10 digits may be used to implement the mostsignificant digits of the counter.

[0027] To summarize, the digit counter may be implemented with variousbase sizes in order to accommodate the minimum count rate and maximumcount required by different applications and to accommodate the variousmaximum erase cycle specifications and size constraints of differentnonvolatile memory devices. Thus, the use of non-uniform base sizespermits the digit counter to be adapted for use in numerous differentapplications and in nonvolatile memory devices having various sizes anderase cycle maximums.

[0028]FIG. 4 illustrates further details of the nonvolatile memorydevice 25 of FIG. 3 according to one embodiment. Preferably, thenonvolatile memory device 25 is a flash EPROM that includes a flash cellarray 41 arranged in discrete blocks. Other types of nonvolatile storagemay be used in alternate embodiments.

[0029] In one embodiment, the nonvolatile memory device 25 includes acommand state machine 31 to receive chip enable (CE#), write enable(WE#) and output enable (OE#) signals from a host device such as amicroprocessor, microcontroller, digital signal processor orapplication-specific processing unit. The command state machine 31 alsoreceives a data input (DATA) either from an internal data buffer 33 orfrom a bi-directional datapath 36 coupled to the host device. Incomingdata is buffered by the data buffer 33 before being written to anaddressable set of storage cells (forming a storage word) in the flashcell array 41. The most significant bits of an incoming address (ADDR)are decoded by a Y-decoder 39 to select a block of storage cells to bewritten to, while lower order bits of the incoming address are decodedby an X-decoder 37 to select a storage word within the selected block.Gating/sensing circuitry 35 enables access the block selected by theY-decoder output. Once the storage word is selected by the X and Ydecoders (37, 39), data is transferred to the storage word from the databuffer 33. In a read operation, the X and Y decoders (37, 39) are usedto select a storage word based on an incoming address as describedabove, then sensing amplifiers within the gating/sensing circuitry 35are used to sense the stored word and pass the word to the data buffer33 for eventual output onto the datapath 36. The nonvolatile memorydevice receives a programming voltage (Vpp), a supply voltage (Vcc) anda ground reference (GND) from off-chip sources. In an alternativeembodiment, the programming voltage may be generated by a charge pumpincluded in the nonvolatile memory device. Also, the command statemachine 31 outputs a ready signal (RDY/BSY#), an alert signal (ALERT)and a maximum count signal (MAX COUNT). The ready signal is used toindicate whether the nonvolatile device 25 is available to carry outhost-requested operations and is typically deasserted, for example,during program and erase operations. The alert and max count signals areoptionally provided to indicate illegal counter-related requests and toindicate when the digit counter has reached a maximum count.

[0030] In one embodiment, the command state machine 31 implements amultiple-bus cycle command structure in which the first bus cycle isused to receive a command from the host and subsequent bus cycles areused to transfer operands, if any, associated with the command. Anexemplary, though not exhaustive, list of commands supported by thecommand state machine 31 is shown in FIG. 5. As shown, a write operationduring a first bus cycle indicates a new command according to the dataassociated with the write operation (i.e., FF hex indicates a readoperation, 90 hex indicates a status read, 50 hex is a command to clearthe status, 40 hex is a command to program a storage word, 20 hex is acommand to erase a block in the array, C0 hex is a counter incrementcommand, and 60 hex is a command to setup the counter). As shown, theread array and program operations involve reading, and writing data froman array address during a second bus cycle. Similarly, the read statuscommand involves reading a status register during a second bus cycle andthe block erase command involves erasing a block of the flash array.

[0031] An increment command 61 and counter setup command 62 are providedto support nonvolatile counter operation. In one embodiment, when anincrement command 61 is received, a counter that is implemented in oneor more of the blocks of the flash array is incremented and theresulting count is automatically returned to the host. In oneimplementation, the count value is returned to the host with the valueof each digit represented by a binary value (e.g., a base₆₅₅₃₆ digit isrepresented by a 16-bit binary number, a base₁₀₂₄ digit is representedby a 10-bit binary value, and so forth). In an alternateimplementations, a pure binary value (i.e., no separate representationof digits) is returned to the host or the raw bit patterns of the digitsthemselves may be returned. In one embodiment, circuitry within thegating/sensing logic 35 is used to generate the binary representation ofthe digits (or of the entire number) returned to the host. In analternate embodiment, logic within the command state machine is used torecord the count value and is updated with each increment command. Whenpower is cycled, the command state machine reads the individual digitsof the counter to recover the count at which power down occurred. Thecommand state machine may record the count value as a binary numberrepresentation of the entire number or as a binary representation of theindividual digits. Also, though not shown in FIG. 5, a separate counterread command may also be provided to read the counter. In that case, thecount value need not be automatically returned in response to theincrement command. Instead, the count may be read by the host whendesired (e.g., under program control).

[0032] In one embodiment, the counter setup command 62 is used toestablish the size of each digit of the digit counter. For example, thesecond bus cycle of the counter setup operation specifies the number ofbits in the first digit, the third bus cycle specifies the number ofbits in the second digit and so forth. In one embodiment, the blockaddress of the first block allocated to a given digit is specified ineach digit setup bus cycle (i.e., in each of the second through Nth buscycles of the counter setup command 62) so that the block in whichdifferent digits of the counter are maintained may be specified by thehost. This allows the digits to be scrambled. Also, the digit base maybe specified by the value transferred on the datapath (i.e., element 36of FIG. 4) during the digit setup bus cycle (i.e., the “DB” value in theDATA column of command 62) so that less than all the bits of a givenblock need be allocated to the digit. For example, a digit setup buscycle in which BA=block 1 and DB=1024, indicates that the first 1024bits of block 1 are to be reserved for a digit of the counter. In oneimplementation, if DB exceeds the number of bits of a block (e.g., blocksize 65536 bits and DB=100,000), then bits in the subsequent block areautomatically allocated to the digit.

[0033] In one embodiment, a region of the flash array (e.g., in block N)is used to record the digit setup information so that, upon powercycling, the structure of the digit counter is recovered. The commandstate machine 31 reads the digit setup information on power up andrecords the boundaries of the digits. Any commands other than legitimatecounter operations (e.g., increment command and, if implemented, readcount command) are screened to ensure that they do not affect the digitsof the digit counter. For example, the command state machine 31 maycompare incoming addresses associated with read, program, erase andother non-counter operations to determine whether the addresses fallwithin an address range (or ranges) allocated to the digit counter. Ifso, the operation is disallowed and, optionally, a security alert signal(e.g., the ALERT signal discussed above) is generated to allow hostprocesses to record the error and take appropriate action. In oneembodiment, the setup information for the digits is recorded in aone-time programmable (OTP) space of the flash array so that it cannotbe altered after initial configuration. By this arrangement, thenonvolatile memory device may be configured to support numerousdifferent secure counting applications either at time offabrication/installation or during to end-user setup. Circuitry forpreventing wrap of the digit counter after the maximum count has beenreached may also be included in the command state machine 31. Also, thecommand state machine 31 may include circuitry to assert the MAX COUNTsignal when the maximum count is reached.

[0034]FIG. 6 is a flow diagram of an increment operation performed bythe command state machine 31 of FIG. 4 according to on embodiment.Initially, a digit pointer (DIGIT) indicative of the digit to beoperated upon is initialized to 1 at block 71. At block 73, a bitpointer (BIT) is also initialized to 1. At decision block 75, the valueof the bit indicated by the bit pointer is evaluated to determine if itis erased (“1”) or programmed (“0”). If erased, then the bit isprogrammed to a “0” at block 76, effectively incrementing the counter.At block 78, digits marked for erasure are erased. The purpose of thisoperation is made clear below. At block 80, the count value of the digitcounter is returned. As discussed above, the count may be read anew fromthe nonvolatile storage in response to each increment command, or thecommand state machine may track the number of increments to the countvalue since the last power up cycle.

[0035] If, at block 75, the value of the bit indicated by the bitpointer is “0,” then the next bit of the digit counter will be checked.Thus, at decision block 81, the bit pointer is compared against the baseof the digit indicated by the digit pointer. If the bit pointer is lessthan the base minus 1, then the bit pointer can be incremented at block83 without indexing past the end of the digit. If the bit pointer is notless than the base minus 1, then all the bits of the digit have beenevaluated (and found to be zero) and the digit pointer (DIGIT) is to beincremented. Accordingly, at decision block 87, the digit pointer iscompared with the number of digits in the digit counter (NUM DIGITS). Ifthe digit pointer is less than NUM DIGITS minus 1, then the digitpointer can be incremented without indexing past the number of digits inthe digit counter. Thus, at block 89, the bits of the digit indicated bythe digit pointer are marked for erasure erased and the digit pointer isincremented to indicate the next digit of the digit counter. By markingthe digit for erasure, rollover of the digit is eventually accomplishedin block 78 after a higher order digit is incremented in block 76. Afterblock 89, processing begins again at block 73, to reinitialize the bitpointer for the newly selected digit to 1.

[0036] If, at decision block 87, the value of the digit pointer is notless than NUM DIGITS minus 1, then the maximum count has been reachedand no further incrementing of the counter is permitted. If thenonvolatile memory device includes a maximum count output, a maximumcount signal is asserted at block 89. Note, that the RDY/BSY or alertoutputs may alternatively be used to transmit the maximum count signal.

[0037] If the maximum count of the counter has not been reached, theneventually an erased bit will be detected in one of the digits of thedigit counter (i.e., at block 75). After the bit is programmed at block76, all digits marked for erasure are erased simultaneously (or at leastnear in time) in block 78. By this design, all digits to be rolled overin a given count increment are rolled over at the same time (or at leastnearly so). Consequently, cumulative erase times are avoided, and delaybetween the program and erase operations is reduced, making the digitcounter less susceptible to corruption arising from power down in themiddle of an increment operation.

[0038] In one embodiment of the present invention, a processor connectedto a monotonic counter, such as processor 102 or security co-processor110 in FIG. 1, can be programmed to automatically configure theabove-described digit counter based on user-provided applicationrequirements and nonvolatile memory device specifications. The processorcalculates an appropriate number of digits and an appropriate base foreach digit based on input maximum count and minimum count raterequirements, and based on timing and erase cycle maximumcharacteristics of the nonvolatile memory device used to implement thecounter.

[0039] The implementation of the non-uniform base digit counter as anon-volatile, monotonic counter ensures that the counter is imperviousto power failures that otherwise might cause a loss of count. The digitcounter is preferably implemented such that higher order digitincrementing occurs before lower order digit erase, and that theoperation completes before the count value is returned. If a countincrement operation is interrupted (such as due to a power failure), thelower order digits may not be fully at a zero state. However, anyintermediate state can be interpreted as being greater than zero, hencea logic one. Thus, the last state of the counter can be effectivelyrecovered.

[0040] In the foregoing specification, the invention has been describedwith reference to specific exemplary embodiments thereof. It will,however, be evident that various modifications and changes may be madethereto without departing from the broader spirit and scope of theinvention as set forth in the appended claims. The specification anddrawings are, accordingly to be regarded in an illustrative rather thana restrictive sense.

What is claimed is:
 1. A counter comprising: a nonvolatile storageorganized in digits having non-uniform bases; and circuitry to incrementa count value represented by the digits in response to an incrementcommand.
 2. The counter of claim 1 wherein the nonvolatile storageincludes a-plurality of blocks of storage cells, each of the digitsbeing stored in a respective one of the blocks.
 3. The counter of claim2 wherein one of the digits spans two or more of the blocks.
 4. Thecounter of claim 2 wherein the nonvolatile storage is a flash erasableprogrammable read only memory in which a selected block of the pluralityof blocks is erased in response to an erase command that identifies theselected block.
 5. The counter of claim 1 wherein each of the digitsincludes a respective number of bits according to its base.
 6. Thecounter of claim 5 wherein the number of bits is equal to the base minusone.
 7. The counter of claim 5 wherein the circuitry to increment thecount value comprises circuitry to increment one digit of the digits byprogramming only one bit of the one digit.
 8. The counter of claim 7wherein the circuitry to increment the one digit of the digits comprisescircuitry to evaluate bits of the one digit to identify a leastsignificant bit of the one digit that is in an erased state, the leastsignificant bit being the only one bit programmed to increment the onedigit.
 9. The counter of claim 1 wherein the circuitry includescircuitry to increment one of the digits and to erase each of the digitsless significant than the one of the digits.
 10. The counter of claim 9wherein the circuitry to erase each of the digits less significant thanthe one of the digits comprises circuitry to concurrently erase each ofthe digits less significant than the one of the digits.
 11. The counterof claim 1 wherein the counter is a down counter and wherein thecircuitry to increment the count value causes the count value to bereduced by one in response to the increment command.
 12. The counter ofclaim 1 wherein the counter is monotonic, the counter further comprisingcircuitry to prevent erasure of the digits in response to detecting thata maximum count of the counter has been reached.
 13. The counter ofclaim 1 further comprising configuration circuitry to receive a countersetup command and to allocate regions of the nonvolatile storage to thedigits according to the counter setup command.
 14. The counter of claim13 wherein the configuration circuitry is configured to store setupinformation specified in the setup command in a region of thenonvolatile storage.
 15. The counter of claim 14 wherein the region ofthe nonvolatile storage where the setup information is stored is aone-time programmable region that cannot be erased.
 16. The counter ofclaim 14 further comprising initialization circuitry to read the setupinformation in the region of the nonvolatile storage to identify thedigits of the counter.
 17. The counter of claim 1 further comprising:program circuitry to write data to the nonvolatile storage in responseto program commands received from an external source; and circuitry todetect whether an address specified by one of the program commands fallswithin a range of the nonvolatile storage allocated to the digits and,if so, to disallow the program circuitry from writing data at theaddress.
 18. The counter of claim 1 further comprising circuitry tooutput the count value represented by the digits in response to theincrement command.
 19. The counter of claim 1 further comprisingcircuitry to output the count value represented by the digits inresponse to a read counter command.
 20. The counter of claim 1 furthercomprising circuitry to generate a binary representation of the countvalue for output to a host processor.
 21. The counter of claim 20wherein the circuitry to generate a binary representation of the countvalue is configured to generate a distinct binary representation of thevalue of each of the digits.
 22. A computer system comprising: a bus; aprocessor coupled to the bus; a nonvolatile memory device coupled to thebus to receive commands from the processor, the commands including anincrement command, the nonvolatile memory device including a nonvolatilestorage array organized in digits having non-uniform bases; andcircuitry to increment a count value represented by the digits inresponse to the increment command.
 23. A computer system comprising: abus; a processor coupled to the bus; a security co-processor coupled tothe bus to receive commands and data from the processor; and anonvolatile memory device coupled to receive commands from the securityco-processor, the commands including an increment, command, thenonvolatile memory device including a nonvolatile storage arrayorganized in digits having non-uniform bases; and circuitry to incrementa count value represented by the digits in response to the incrementcommand.
 24. A method comprising: receiving a command to increment acounter implemented in a nonvolatile storage device, the nonvolatilestorage device including a nonvolatile storage array organized in digitsthat have non-uniform bases, the digits defining the counter; searchingeach of the digits in order of significance until a least significantunprogrammed bit of one of the digits is found; and programming theunprogrammed bit to carry out the increment command.
 25. The method ofclaim 24 further comprising erasing bits of each of the digits lesssignificant than the one of the digits containing the unprogrammed bitto carry out the increment command.
 26. The method of claim 24 furthercomprising receiving a command specifying a base for each of the digitsof the counter.
 27. The method of claim 24 further comprising receivinga command specifying a quantity of the digits.